1. Field of the Invention
The present invention relates to start-up circuits for initializing logic circuits to a defined state. More specifically, the present invention relates to start-up circuits for usage in various memories and storages that initialize and hold a node to a preferred state unless overridden.
2. Description of the Related Art
Digital circuits such as microprocessors typically include system logic that responds to the application of operating power by resetting the microprocessor to a known state and asserting a RESET signal. The microprocessor samples the asserted RESET signal and immediately flushes and initializes all internal resources and the microprocessor internal state including the state of pipelines, caches and tag memories, the floating-point state, the state of special purpose processors such as a Multi-Media eXtension (MMX) processor, and all registers. The microprocessor typically jumps to a preset program address to being instruction execution.
The system power-up logic includes power-up initialization circuits that first place the digital circuits into a known state. Some digital circuits include self-resetting type logic for holding a circuit element to a known state without the usage of a dedicated reset signal. Unfortunately, the element must be held to a specified state. If the element powers up in the wrong state, the microprocessor is typically unable to initialize or initialization is extended to a long duration that consumes power.
Power-up initialization circuits are generally divided into two classes. A first class of power-up initialization circuits ensures that a node is placed in a predetermined state, generally either a digital high (VDD) state or a digital low (VSS) state, upon application of power to a circuit. A second class of power-on initialization circuits emits a momentary pulse of a selected time duration during power-up, then returns to a steady quiescent state.
For the first class of power-up initialization circuits, a node is placed in the predetermined state upon power-up usually by applying an increasing voltage to a gate of a transistor as the power supply voltage gradually increases in a linear ramp fashion. The power supply may ramp up at a wide range of rates. One of the problems addressed by the first class of power-up initialization circuit is the difficulty of achieving a consistent, robust response over a wide range of power-on ramping rates of the power supply.
The difficulty of attaining a suitable power-up initialization response is compounded for large and complex integrated circuits such as microprocessors. Microprocessors include many complex and highly diverse circuit portions that generate competing electrical effects, mainly capacitive coupling at various nodes in the integrated circuit, while devices are operating in the subthreshold voltage region. These competing electrical effects are sometimes critical to circuit performance.
For example, many storage or memory circuits include equilibrate lines that charge selected lines of bit and bit-bar (inverse logic) lines to the voltage supply reference VDD. The memory circuits also include write select lines that discharge selected lines of the bit and bit-bar lines to a reference VSS. However, unless the equilibrate and write select lines start-up in a defined suitable state, the multiple bit lines draw current in parallel, potentially causing a low enough impedance between the voltage supply reference VDD and the VSS reference power rails that the circuit fails to attain an adequate differential to operate the memory circuit and reset the equilibrate lines. Consequently, the integrated circuit never initializes and simply expends power uselessly.
One technique for placing the memory in a suitable state that does not waste power is to perform an initialization operation that performs a dummy read cycle. Unfortunately, the circuit may power-up in a state that does not allow the initialization operation to take place.
What is needed is a power-up initialization circuit that ensures designated internal circuit nodes are set in selected states within a suitable time duration. What is needed is a circuit and operating method for initializing nodes of a circuit to a known state during a power-up transient. What is further needed is a power-up initialization circuit and technique that performs initialization without activation of special reset signals. What is additionally needed is a power-up initialization circuit and operating method that guarantees the setting and maintaining of nodes to the known state.